- Evaluation of fault injection tools for reliability estimation of microprocessor-based embedded systems.
Autores: Alexander Aponte-Moreno, José Isaza-González, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle.
Microprocessors and Microsystems 96, 104723. DOI:https://doi.org/10.1016/j.micpro.2022.104723
- Availability and Use of ICTs in Rural Areas in Panamá: Tulú Case Study. Autores: Yarisel Núñez-Bernal, Ismael Camargo-Hernríquez, José Isaza-Gonzalez, Juan Castillo.
2022 8th International Engineering, Sciences and Technology Conference (IESTEC). DOI: 10.1109/IESTEC54539.2022.00048
- ITC-based Municipal Disaster Risk Management: Panama Case Study. Autores: Elvira Meléndez, José Iván Isaza-González, Juan Castillo, Ricardo González, Ignacio Chang, Antony García.
Universidad Tecnológica de Panamá, Panamá. DOI: https://doi.org/10.33412/idt.v17.2.3479
- An experimental comparison of fault injection tools for microprocessor-based systems. Autores: Alexander Aponte-Moreno, José Isaza-González, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Felipe Restrepo-Calle.
2020 IEEE Latin-American Test Symposium (LATS), 1-6. DOI: 10.1109/LATS49555.2020.9093668
- SHARC: An efficient metric for selective protection of software against soft errors. Autores: José Isaza-González, Felipe Restrepo-Calle, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi.
Microelectronics Reliability 88, 903-908. DOI: https://doi.org/10.1016/j.microrel.2018.07.008
- Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación. Autor: José Isaza-González. Repositorio Tesis Doctoral. Universidad de Alicante.
- Contrast of a HDL model and COTS version of a microprocessor for Soft-Error Testing. Autores: José Isaza-González, Alejandro Serrano-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Hipólito Guzmán-Miranda, Miguel A Aguirre.
2017 18th IEEE Latin American Test Symposium (LATS), 1-6. DOI: 10.1109/LATW.2017.7906771
- Evaluación de la fiabilidad de microprocesadores COTS mediante las infraestructuras de depuración On-Chip. Autores: José Isaza-González, Alejandro Serrano-Cases, Felipe Restrepo Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez.
Universidad Tecnológica de Panamá
- On the influence of compiler optimizations in the fault tolerance of embedded systems. Autores: Alejandro Serrano-Cases, José Isaza-González, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez. 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS). DOI: 10.1109/IOLTS.2016.7604701
- Dependability evaluation of COTS microprocessors via on-chip debugging facilities. Autores: José Isaza-González, Alejandro Serrano-Cases, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez. 2016 17th Latin-American Test Symposium (LATS), 27-32. DOI: 10.1109/LATW.2016.7483335
